Abstract: In SoCs, static random-access memory (SRAM) occupies 60% of its area. Under nanoscale CMOS technology at lower supply voltages and technology nodes, the MOSFET undergoes various short channel effects and the design of the SRAM cell becomes progressively challenging due to increased leakage power consumption and degraded data stability. Therefore, it is very important to overcome those limitations and improve its performance. This paper presents the design of a 6T SRAM cell using new technologies like FinFET, CNTFET and GNRFET at different nodes to improve the performance in terms of leakage power and stability. All the design simulations are carried out using the SYNOPSIS HSPICE tool at different technology nodes with appropriate power supplies. Performance characteristics of the CMOS 6T SRAM cell is compared with FinFET, CNTFET, and GNRFET technologies based 6T SRAM cells. Results analysis shows that CNTFET based 6T SRAM cells achieve greater stability than other designs whereas GNRFET based 6T SRAM cells dissipate less power than other designs. Therefore, this paper concludes that the new technology-based 6T SRAM cell design offers greater stability and lower leakage power, which is suitable for low power applications.

Key words: accuracy, SRAM, CMOS, FinFET, CNTFET GNRFET, HSPICE