Int J Performability Eng ›› 2023, Vol. 19 ›› Issue (3): 167-174.doi: 10.23940/ijpe.23.03.p2.167174

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Low Power Full Adders based on Proposed Hybrid and GDI Designs: A Novel Approach

Anubhav Anand, Satyam Singh, Sandeep Dhariwal*, Reeba Korah, and Gaurav Kumar   

  1. Alliance College of Engineering and Design, Alliance University, Bengaluru, Karnataka, 562106, India
  • Contact: * E-mail address:

Abstract: This research article provides proposed designs of hybrid and GDI-based full adders with better performance parameters, such as power dissipation, propagation delay, and power delay product. Performance analysis of the existing designs and proposed designs are carried out for one-bit full adder using industry standard Cadence tool, Virtuoso at 45nm with a 1V supply. Based on the survey of performance, the best existing full adder designs are taken into consideration. These existing designs are based on GDI and hybrid techniques. The simulation results show that the proposed design performs better in terms of power dissipation and delay. The GDI-based proposed full adder exhibits less power dissipation compared to the existing GDI full adder. On the other hand, the hybrid-based proposed full adder also exhibits less power dissipation compared to the existing hybrid full adder. Among these two proposed techniques, the hybrid technique is much better in terms of power consumption, and the delay is less compared to existing designs. Therefore, these proposed designs can be considered for power efficient ALUs and processors.

Key words: full adder (FA), transmission gate, pass transistor, GDI, low transistor count, ALU, hybrid