Int J Performability Eng ›› 2021, Vol. 17 ›› Issue (6): 511-518.doi: 10.23940/ijpe.21.06.p3.511518
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V. Nandhini* and K. Sambath
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* E-mail address: nandhiniresearch2020@gmail.com
V. Nandhini and K. Sambath. Implementation of Normal Urdhva Tiryakbhayam Multiplier in VLSI [J]. Int J Performability Eng, 2021, 17(6): 511-518.
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1. Swami J., Krisna S. B., Maharaja T., 2. Mano M.M., 3. Thapliyal, H. and Arabnia, H.R., A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. In 4. Ashwath, M. and Premananda, B.S., Signed Fixed-Point Multiplier for DSP Using Vertically and Crosswise Algorithm. In 5. Tiwari H.D., Gankhuyag G., Kim C.M., andCho Y.B., Multiplier Design Based on Ancient Indian Vedic Mathematics. In 6. Chidgupkar, P.D. and Karad, M.T., The Implementation of Vedic Algorithms in Digital Signal Processing. 7. Thapliyal, H. and Srinivas, M.B., High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics. 8. Dhillon, H.S. and Mitra, A. A., Reduced-Bit Multiplication Algorithm for Digital Arithmetic. 9. Yogendri and Gupta, A.K., Design of High Performance 8-Bit Vedic Multiplier. In 10. Patil H.P., andSawant S.D., FPGA Implementation of Conventional and Vedic Algorithm for Energy Efficient Multiplier. In 11. Sharma R., Kaur M., andSingh G., Design and FPGA implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures. In 12. Kumar U.P., Goud A.S., andRadhika., A. FPGA Implementation of High Speed 8-Bit Vedic Multiplier Using Barrel Shifter. In 13. Dixit H.V., Kasat P.S., Balwaik R., andJeyakumar A. A., Parallel Pipelined Approach to Vedic Multiplier for FPGA implementation. In 14. Paramasivam, M.E. and Sabeenian, R.S., An Efficient Bit Reduction Binary Multiplication Algorithm Using Vedic Methods. In 15. Premananda B.S., Pai S.S., Shashank B., andBhat S.S., Design and Implementation of 8-Bit Vedic Multiplier. 16. Mehta, P. and Gawali, D., Conventional Versus Vedic Mathematical Method for Hardware Implementation of A Multiplier. In 17. More, T.V. and Panat, A.R., FPGA Implementation of FFT Processor Using Vedic Algorithm. In 18. Anjana R., Abishna B., Harshitha M.S., Abhishek E., Ravichandra V., andSuma M.S., Implementation of Vedic Multiplier Using Kogge-Stone Adder. In 19. Sangani H., Modi T.M., andBhaaskaran V.K., Low Power Vedic Multiplier Using Energy Recovery Logic. In |
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