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, No 6

■ Cover page(PDF 3.15 MB) ■  Table of Content, Jun 2021  (PDF 35 KB) 

  • Dynamic Flow Scheduling Technique for Load Balancing in Fat-Tree Data Center Networks
    Wen-Hsuan Liang, Dun-Wei Cheng, Chih-Wei Hsu, Chia-Wei Lee, Chih-Heng Keand, Albert Y. Zomaya, and Sun-Yuan Hsieh
    2021, 17(6): 491-503.  doi:10.23940/ijpe.21.06.p1.491503
    Abstract    PDF (1141KB)   
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    Modern data center networks for a fat-tree topology typically adopt a multirooted hierarchical tree structure to achieve multiple-path capability and increase bisection bandwidth. However, the performance of a data center network highly depends on the routing protocols. Conventional routing protocols are unsuitable for modern data center topologies because they lack multiple-path routing support. Another crucial concern in data center networks is load balancing. Certain routing protocol limitations could lead to overloaded or underloaded utilization of a link, thereby considerably reducing the performance of a data center network. Therefore, we present a genetic algorithm (GA)-based dynamic load-balancing routing algorithm, which is heuristic and involves the use of a centralized scheduling technique. This algorithm mainly uses a GA to search for optimal solutions. We implement our algorithm in an OpenFlow controller RYU and Mininet emulator, which is based on software-defined networking architecture. Our evaluation results revealed that our algorithm can effectively achieve load balancing and increase bisection bandwidth.
    An Integrated System for Initial Prediction of Autism Spectrum Disorder
    Azhagiri.M, Shubhanjay Mishra, Shubham Joshi, and Amritash Srivastava
    2021, 17(6): 504-510.  doi:10.23940/ijpe.21.06.p2.504510
    Abstract    PDF (384KB)   
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    Autism Spectrum Disorder (ASD) neuro-developmental disarray incorporates numerous conduct issues like socializing and lack of communication. The traits of autism tend to show during early childhood and regularly last all through an individual's life. The symptoms include avoiding eye contact, needing to be separated from everyone else, and experiencing difficulty identifying with others or not having an interest in others. It also includes conditions like recursive examples of conduct, territories of interest, or exercises. A framework to record, identify and label the different patterns of conduct of people with ASD has been created. In this study, various sorts of classification methods for ASD diagnosis were used on the dataset consisting of people from different age groups. The classification techniques that we used were LDA (Linear Discriminant Analysis), Logistic regression and KNN (KNearest Neighbor). Using these methods, the findings suggest that the model performed best using Logistic Regression to predict Autism Spectrum Disorder with a precision of 99% during the validation trial.
    Implementation of Normal Urdhva Tiryakbhayam Multiplier in VLSI
    V. Nandhini and K. Sambath
    2021, 17(6): 511-518.  doi:10.23940/ijpe.21.06.p3.511518
    Abstract    PDF (354KB)   
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    Presently, low-power VLSI configuration is pulling in all the electronic gadgets since power turned into a significant basis in planning. Today, practically the entirety of the electronic gadgets is being utilized in battery reinforcement for compactness and comfort. This low force utilization will likewise help in decreasing heat dissipation in such electronic gadgets bringing about wide and long use. Multipliers are utilized generally in advanced sign handling applications. An effective plan of the multiplier has been planned. Since multipliers are an essential part of a large portion of electronic gadgets. A mix of the multiplier is dependent on the specific boundaries like area, speed, and power in which VLSI configuration should be concentrated. In this paper, the normal VLSI multiplier architecture has been implemented for 2×2, 4×4, 8×8, 16×16, and 32×32 bits using a conventional logic gate. The performance is evaluated by the power, delay, and area of each multiplier circuit design. Simulations are carried out for series target boards and results are compared with multipliers implemented with other VLSI multiplier architecture.
    Analysis of the Criteria for Assessing the Forecast Quality of Industrial Safety Indicators of Enterprises
    Leila M. Bogdanova, Sergey Ya. Nagibin, and Alexander S. Chemakin
    2021, 17(6): 519-527.  doi:10.23940/ijpe.21.06.p4.519527
    Abstract    PDF (601KB)   
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    The paper describes changes of paradigm management in enterprise’s industrial safety based on a risk-based approach. This method includes identifying, analyzing, forecasting the risks of industrial accidents as well as assessing the possible extent of their consequences. All calculations should be made in a timely manner to take the necessary measures to prevent accidents. The technological complexity of enterprises is a complex system consisting of various components. The risks of failure of these components pose a security risk. Critical enterprises monitoring systems are introduced in order to increase the level of safety. These systems monitor the state of the nodes of the technological complex and predict the behavior of key indicators for a given period. The effectiveness of industrial safety management depends on the accuracy of these predictions. Various methods can be used to assess forecast. The purpose of this paper is to analyze the criteria used to assess the quality of forecast models and recommendations for their usage in practical life. Various coefficients based on residuals are used to assess the applicability of a particular model. As shown in the results of our research, not all indicators should be used in industrial safety systems. This paper describes the results of the possibility for using various coefficients in training forecast models and for demonstrating an empirical assessment of the model.
    Collaborative and Early Detection of Email Spam using Multitask Learning
    Balika J. Chelliah, Anand Sasidharan, Dharmesh Kumar Singh, and Nilesh Dangi
    2021, 17(6): 528-535.  doi:10.23940/ijpe.21.06.p5.528535
    Abstract    PDF (273KB)   
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    Email spam has become a huge nuisance in the last couple of years. It not only wastes valuable time, but is also extremely dangerous as well. The various solutions that exist to detect spam use a manual input of keywords or filtering of particular domains. No matter the amount of filtering, it is quite tedious and difficult to check for spam. This paper includes a unique solution that attempts to use deep neural networks, a machine learning technique which detects any pattern of recurrent words which may have been classified as spam. Every other parameter of the email is examined as a feature and applied accordingly to the machine learning algorithm. Deep neural networks are quite advanced and can easily differentiate between a proper and an improper output.
    Carry Select Adder Design with Testability using Reversible Gates
    S. Rooban, D. Lakshmi Prasanna, K.B.S. Durga Teja, and P.V. Mani Kumar
    2021, 17(6): 536-542.  doi:10.23940/ijpe.21.06.p6.536542
    Abstract    PDF (491KB)   
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    A concurrent detectable carry select adder using reversible gates is proposed. The carry select adder is implemented with reversible gates, which include peres gates, Toffoli gates, and Feynman gates. The reversible gates detect the faults concurrently. The error occurred due to faults identified by analysingthe predicted parity of the sum with the actual parity of sum. This concurrent carry select adder is tested using 10 input patterns with different radix number system. This concurrent feature enables the carry select adder to identify the fault before the occurrence of a second fault. A novel approach for concurrent error detectability of a carry select adder and the easy testability of the carry select adder are implemented. A 64-bit carry select adder using reversible gate is designed with Verilog HDL in VLSI technology; simulation and synthesis are performed using XILINX ISE.
    Fast Computational Efficient Directional Shrinking Search Optimization Algorithm
    D.P. Tripathi, Mahesh Nayak, Rajaboina Manoj, Surarapu Sudheer, and K. Praghash
    2021, 17(6): 543-551.  doi:10.23940/ijpe.21.06.p7.543551
    Abstract    PDF (626KB)   
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    In this paper, a novel fast heuristic optimization algorithm has been proposed that effectively boosts the exploration and exploitation process during the search of a global optimum in the search region. In this proposed algorithm, a particle position dependent stochastic variable is used to control the exploration and exploitation process. It is also used to reduce the computational time requirement. The search region shrinks efficiently in a continuous manner during successive iterations. The performance of the algorithm has been validated by comparing the simulation results of the particle swarm optimization (PSO), quantum particle swarm optimization (QPSO) and firefly algorithm (FFA) using some well-known benchmark functions. The proposed algorithm reduces the computational time around 44.2% compared to others in finding the global optimum point.
    FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm
    Barma Venkata RamaLakshmi and Fazal Noorbasha
    2021, 17(6): 552-558.  doi:10.23940/ijpe.21.06.p8.552558
    Abstract    PDF (268KB)   
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    Multipliers play a key role in performance of any system. However, the major drawback is it consumes more power and area. To enhance the performance and decrease the power consumption and area consumption, there are many algorithms and techniques. In any multiplication algorithm, the main aim is to decrease the partial product summation. One of the widely used and effective algorithms is the booth algorithm. In this paper, we are designing and implementing the radix 4 and radix 8 booth algorithm. In the radix 4 algorithm, the partial products are reduced to n/2, whereas in the radix 8 algorithm, we can reduce the partial products to n/3 in the multiplier encoding. The simulation results are carried out on the Xilinx Vivado tool.
    Investigation of Growth Management and Field Optimization on IOT-based Technology for Chilli Cultivation: Hybrid Chilli (F1 Golden Parrot) in Pallavolu, Nellore
    Ngangbam Phalguni Singh, Sabbisetty Akhil, Ratakonda Vishnu, K. Kirit Redddy, B. Bhanu Prakash, and Shruti Suman
    2021, 17(6): 559-568.  doi:10.23940/ijpe.21.06.p9.559568
    Abstract    PDF (599KB)   
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    Andhra Pradesh is one of the leading chilli producing states in India and Asia. However, many farmers experience low yields due to various reasons such as pests and excess water during cultivation. In agriculture, the methods are now data-centric. It involves exploring poor performance and finding appropriate solutions. The rapidly growing applications of Internet-of-Things (IoT) based technology are attracting farmers to adopt smart farming, which is changing the system from qualitative approaches to quantitative approaches. This opens a door for our undertaking to include the abilities of different sensors for IoT in rural areas. Hybrid chilli (F1 Golden parrot) has been selected for cultivation in the Pallavolu area of Nellore. Therefore, weather conditions and provocation for this mission in this area will be deliberated. IoT tools and communication technologies related to sensors in agricultural applications are analyzed in detail. Moreover, an appropriate approach to monitoring crop health and field optimization will be studied in this project. High quality and improved production of hybrid chilli (F1 Golden Parrot) is expected in the Pallavolu area of Nellore.
ISSN 0973-1318