Design and Analysis of Power and Area Efficient Novel Concurrent Cellular Automation Logic Block Observer BIST Structure

doi:10.23940/ijpe.20.01.p3.1926

Abstract

Abstract:

This paper presents a novel architecture named as Concurrent Cellular Automation Logic Block Observer (CCALBO) BIST structure. This technique is a combined result from the designs of CBILBO (Concurrent Built In Logic Block Observer) and CALBO (Cellular Automation Logic Block Observer). Architecture of designing the CCALBO cell and its fault masking probability with inclusion in a combination and sequential CUT has been considered. Vedic Multiplier and Multiply & Accumulate Unit (MAC) are used as circuit under test (CUT). CCALBO-based BIST is compared with most competitive technique CBILBO-based BIST. Major parameters such as power and area have been considered. Compared to CBILBO technique, CCALBO-based BIST has presented significant dynamic power reduction using Vedic multiplier and MAC unit as circuit under test (CUT). It has been observed that area also gets reduced in the novel CCALBO design, because parallel in parallel out (PIPO) registers are used to generate scan chains in test logic. CCALBO-based BIST has been found to achieve fault coverage of 100% in lesser duration as compared to CBILBO. Overall, CCALBO is better over CBILBO in the major aspects of area and low power dissipation and more reliable with respect to testing.

Key words: BILBO, BIST, CALBO, CBILBO, CAR, CCALBO, MAC, Vedic multiplier

Sandeep Dhariwal and Ravi Trivedi. Design and Analysis of Power and Area Efficient Novel Concurrent Cellular Automation Logic Block Observer BIST Structure [J]. Int J Performability Eng, 2020, 16(1): 19-26.

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Figures/Tables 18

Rule 90 : x j t + 1 = x j - 1 t + x j + 1 t

(1)

Rule 150 : x j t + 1 = x j - 1 t + x j t + x j + 1 t

(2)

Figure 1.

Figure 2.

Figure 3.

Figure 5.

P CCALBO = 2 m - 1 - 1 2 m + n - 1 - 1 × 100 %

(3)

Figure 6.

P CCALBO = 2 m - 1 - 1 2 m + n - 1 - 1 × 100 % = 1 2 n × 100 %

(4)

Figure 7.

Figure 8.

Figure 9.

Table 1

Table 2

Figure 10.

Figure 11.

Table 3

Table 4

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BIST structure	Vedic multiplier (VM) BIST	Vedic multiplier (VM)	Test logic
CCALBO	1715390nW	976890nW	64600nW
CBILBO	3167100nW	2341680nW	131900nW

BIST structure	MAC BIST	Vedic multiplier (VM)	Carry skip adder	Test logic
CCALBO	121900nW	4390nW	10110nW	6100nW
CBILBO	359300nW	205699nW	62900nW	46650nW

BIST structure	Vedic multiplier (VM) BIST	Vedic multiplier (VM)	Test logic
CCALBO	1534	1079	410
CBILBO	1400	11040	91

BIST structure	MAC BIST	Vedic multiplier (VM)	Carry skip adder	Test logic
CCALBO	1370	888	87	60
CBILBO	1411	1049	145	78

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