Int J Performability Eng ›› 2019, Vol. 15 ›› Issue (11): 3052-3060.doi: 10.23940/ijpe.19.11.p25.30523060

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Design of Register File for Negative Bias Temperature Instability

Yuanyuan Maa, Bai Naa,*, Wei Tanb, and Gelan Yangc   

  1. aSchool of Electronic and Information Engineering, University of Anhui of China, Hefei, 230601, China;
    bSchool of Computer Science and Technology, Dongguan University of Technology, Dongguan, 523808, China;
    cDepartment of Computers, Hunan City University, Yiyang, 413000, China
  • Submitted on ; Revised on ; Accepted on
  • Contact: * E-mail address: bnasic@126.com

Abstract: Negative bias temperature instability (NBTI) is becoming an important reliability problem in the semiconductor industry. As time goes on, the NBTI aging impact affects microprocessors' ability to perform correct calculations. The SRAM-based register file block is one of the largest logic units, and it is affected by process deviations. SRAM is the bottleneck of the whole process deviation tolerance. Based on theoretical analysis, the connection between the SRAM static noise margin value and the bitcell probability is discussed. Moreover, this paper adopts a dynamic shifter combined with periodic bitcell inversion design to reduce the NBTI aging impact and achieve a more robust register file. Simulation results exhibit that this design improves the bitcell probability by 3.7 times and reduces the uncertainty of SNM caused by NBTI stress to 46.79%.

Key words: negative bias temperature instability, architecture register file, static noise margin, bias probability