Int J Performability Eng ›› 2021, Vol. 17 ›› Issue (6): 552-558.doi: 10.23940/ijpe.21.06.p8.552558

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FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm

Barma Venkata RamaLakshmi and Fazal Noorbasha*   

  1. Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, 522502, India
  • Contact: * E-mail address:

Abstract: Multipliers play a key role in performance of any system. However, the major drawback is it consumes more power and area. To enhance the performance and decrease the power consumption and area consumption, there are many algorithms and techniques. In any multiplication algorithm, the main aim is to decrease the partial product summation. One of the widely used and effective algorithms is the booth algorithm. In this paper, we are designing and implementing the radix 4 and radix 8 booth algorithm. In the radix 4 algorithm, the partial products are reduced to n/2, whereas in the radix 8 algorithm, we can reduce the partial products to n/3 in the multiplier encoding. The simulation results are carried out on the Xilinx Vivado tool.

Key words: Booth multiplier, Booth algorithm, radix 4, radix 8, encoding, partial product