Int J Performability Eng ›› 2021, Vol. 17 ›› Issue (6): 536-542.doi: 10.23940/ijpe.21.06.p6.536542

Previous Articles     Next Articles

Carry Select Adder Design with Testability using Reversible Gates

S. Rooban*, D. Lakshmi Prasanna, K.B.S. Durga Teja, and P.V. Mani Kumar   

  1. Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, 522502, India
  • Contact: * E-mail address:

Abstract: A concurrent detectable carry select adder using reversible gates is proposed. The carry select adder is implemented with reversible gates, which include peres gates, Toffoli gates, and Feynman gates. The reversible gates detect the faults concurrently. The error occurred due to faults identified by analysingthe predicted parity of the sum with the actual parity of sum. This concurrent carry select adder is tested using 10 input patterns with different radix number system. This concurrent feature enables the carry select adder to identify the fault before the occurrence of a second fault. A novel approach for concurrent error detectability of a carry select adder and the easy testability of the carry select adder are implemented. A 64-bit carry select adder using reversible gate is designed with Verilog HDL in VLSI technology; simulation and synthesis are performed using XILINX ISE.

Key words: carry select adder, concurrent error detectability, reversible gates, Toffoli gates