Int J Performability Eng ›› 2020, Vol. 16 ›› Issue (3): 325-332.doi: 10.23940/ijpe.20.03.p1.325332

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Delay Reduction by Implementation of Voltage-Controlled Ring Oscillator with Reverse Substrate Bias

Ravi Shankar Mishraa and Sandeep Dhariwalb,*   

  1. aElectronics & communication Engineering, Guru Nanak Institute of Technology, Hyderabad, India;
    bAlliance College of Engineering and Design, Alliance University, Bengaluru, Karnataka, 562106, India
  • Submitted on ; Revised on ; Accepted on
  • Contact: Sandeep Dhariwal

Abstract: In this work, different ring VCO topologies and architectures are designed to improve the performance of the conventional VCO structure. A single-ended ring VCO is designed and implemented at different control voltages. The output frequency range observed is between 3.27 and 12.57 GHz with the control voltage ranging from 1 V to 0.5 V. The minimum delay measured is 17.8 picoseconds. The other architecture involves the reverse substrate-bias (SB) technique and differential structure for further improvement of the performance parameters of the VCO. All the topologies are designed in Cadence Virtuoso with gpdk 90 nm technology. The differential structure and reverse SB structure result in frequency ranges of 17.405 GHz to 10.982 GHz and 11.87 GHz to 13.77 GHz, respectively. The results demonstrate a minimum delay, and the power consumptions are 8.1 picoseconds and 62.42 µW for the differential configuration and 8.27 picoseconds and 32.96 µW for the reverse-substrate bias technique, respectively. Overall, the voltage-controlled ring oscillator with reverse substrate bias is most suitable for delay reduction.

Key words: VCO, frequency response, Cadence Virtuoso, power consumption, differential configuration, substrate bias