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UCM: A Novel Approach for Delay Optimization

Volume 15, Number 4, April 2019, pp. 1190-1198
DOI: 10.23940/ijpe.19.04.p14.11901198

Rajkumar Sarmaa, Cherry Bhargavaa, Sandeep Dhariwalb, and Shruti Jainc

aSchool of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, 144411, India
bAlliance College of Engineering and Design, Alliance University, Bengaluru, Karnataka, 562106, India
cDepartment of Electronics and Communication Engineering, Jaypee University of Information Technology, Waknaghat, Himachal Pradesh, 173234, India

 

(Submitted on December 25, 2018; Revised on December 27, 2018; Accepted on April 15, 2019)

Abstract:

In the era of digital signal processing, such as graphics and computation systems, multiplication is one of the prime operations. A multiplier is a key component in any kind of digital system such as Multiply-Accumulate (MAC) unit, various FFT algorithms, etc. The efficiency of a multiplier is mainly dependent upon the speed of operation and power dissipation of the circuit along with the complexity level of the multiplier. This paper is based on Universal Compressor based Multiplier (UCM), which yields a high-speed operation with comparative power dissipation; hence, the enhanced performance is reported. The novel design of UCM is analyzed using Cadence Spectre tool in 90nm CMOS technology. Finally, the UCM is implemented using Nexys-4 Artix-7 FPGA board. The novel design of UCM has demonstrated significant improvement in terms of delay, which is explored in this paper.

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