Improving the Performance of Multi-Mode SM4 Block Cipher

doi:10.23940/ijpe.19.10.p4.25892596

Int J Performability Eng ›› 2019, Vol. 15 ›› Issue (10): 2589-2596.doi: 10.23940/ijpe.19.10.p4.25892596

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Improving the Performance of Multi-Mode SM4 Block Cipher

Guangyong Hu^* and Rui Chen

School of Computer and Software Engineering, Nanjing Institute of Industry Technology, Nanjing, 210023, China

Submitted on ; Revised on ; Accepted on
Contact: Hu Guangyong
About author:
* Corresponding author. E-mail address: hugy@niit.edu.cn

Abstract

Abstract:

In this paper, a low-cost multi-mode hardware architecture is proposed for data confidentiality of resource-constrained IoT (Internet of things) devices. The proposed architecture adopts resource sharing technologies to reduce the number of s-boxes, eliminate memory requirement of expanded keys, and realize flexible reconfigurability of various operation modes. The FPGA implementation results show that only 1,326 LUTs and 1,000 registers are needed at 50MHz. Compared with related works, resource costs are reduced significantly.

Key words: resource-constrained, internet of things, block cipher, SM4, FPGA

Guangyong Hu and Rui Chen. Improving the Performance of Multi-Mode SM4 Block Cipher [J]. Int J Performability Eng, 2019, 15(10): 2589-2596.

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Improving the Performance of Multi-Mode SM4 Block Cipher

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