FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm

doi:10.23940/ijpe.21.06.p8.552558

Abstract

Abstract: Multipliers play a key role in performance of any system. However, the major drawback is it consumes more power and area. To enhance the performance and decrease the power consumption and area consumption, there are many algorithms and techniques. In any multiplication algorithm, the main aim is to decrease the partial product summation. One of the widely used and effective algorithms is the booth algorithm. In this paper, we are designing and implementing the radix 4 and radix 8 booth algorithm. In the radix 4 algorithm, the partial products are reduced to n/2, whereas in the radix 8 algorithm, we can reduce the partial products to n/3 in the multiplier encoding. The simulation results are carried out on the Xilinx Vivado tool.

Key words: Booth multiplier, Booth algorithm, radix 4, radix 8, encoding, partial product

Barma Venkata RamaLakshmi and Fazal Noorbasha. FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm [J]. Int J Performability Eng, 2021, 17(6): 552-558.

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References

1. Baig, N. and Noorbasha, F.CMOS low voltage LNA with improved noise figure.International Journal of Innovative Technology and Exploring Engineering, 8(6), pp.606-609, 2019.
2. Baig, N. and Noorbasha, F. Ultra-wide band LNA design using active inductor with modified noise cancellation technique, International Journal of Recent Technology and Engineering (IJRTE), ISSN:2277-3878, 8(2), pp. 2406-2410, 2019.
3. Mandrumaka, K.K. and Noorbasha, F.A low power 10 bit SAR ADC with variable threshold technique for biomedical applications.SN Applied Sciences, 1(8), pp.1-9, 2019.
4. Kumar, M.K., Noorbasha, F. and Rao, K.S.Design of low power 16X16 SRAM array using GDI logic with dynamic threshold technique.ARPN Journal of Engineering and Applied Sciences, 12(22), pp.6571-6576, 2017.
5. Pragathi B., Veramalla R., Noorbasha F. and Jampana B.Power quality improvement for grid interconnected solar PV system using neural network control algorithm.International Journal of Power and Energy Conversion, 9(2), pp.187-204, 2018.
6. Blessington P.,Bhaskara B., and Noorbasha, Fazal. Estimation of latency and throughput for three-dimensional network-on-chip architecture, Journal of Advanced Research in Dynamical and Control Systems, 10(7)(Special Issue), pp. 1353-1359, 2018.
7. Kishore K.H., Noorbasha F., Sandeep K., Bhupesh D.N.V., Khadar Imran SK., and Sowmya, K. Linear convolution using UT Vedic multiplier, International Journal of Engineering and Technology(UAE), ISSN No: 2227-524X, 7(2.8), pp.409-418, 2018.
8. Reyaan S.M., Venkat B. M., Shankar G.Y.V.S., Kishore K.H., Noorbasha F., Archana Y., andRazia, S. Power Analysis of FIR Filter Design Using APC-OMS Algorithm, Journal of Advanced Research in Dynamical and Control Systems, ISSN No: 1943-023X, 12(2), pp. 1085-1092, 2020.
9. Anitha, A., Rooban, S. and Sujatha, M.Implementation of energy efficient gates using adiabatic logic for low power applications.International Journal of Recent Technology and Engineering, 8(3), pp.3327-3332, 2019.
10. Rooban S., Kumar K.S., Shankar K.R. and Bhaskara Rao, N.U. Test and analysis of high performance microprocessor through power binning method.International Journal of Engineering and Advanced Technology, 8(4), pp.882-886, 2019.
11. Rooban S., Saifuddin S., Leelamadhuri S. and Waajeed S.Design of fir filter using wallace tree multiplier with kogge-stone adder.International Journal of Innovative Technology and Exploring Engineering, 8(6), pp.92-96, 2019.
12. Rooban, S. and Manimegalai, R.Prediction of Theoretical Limit for Test Data Compression. In 2018 International Conference on Recent Trends in Advance Computing (ICRTAC) (pp. 41-46). IEEE, 2018.
13. Soumya N., Kumar K.S., Rao K.R., Rooban S., Kumar P.S. and Kumar G.N.S., 4-Bit Multiplier Design using CMOS Gates in Electric VLSI.International Journal of Recent Technology and Engineering (IJRTE) ISSN, pp.2277-3878, 2019.
14. Rooban, S, Swathi K.L., Monica C., andShivaramakrishna B.An odd parity genertor design using nano-electronics,International Journal of Engineering and Advanced Technology, 8(4), pp. 597-601, 2019
15. Rooban S., Chowdary B.N., Vinay B. and MVS S.S.Design of school bus subscription authentication and management system using face recognition technology.International Journal of Innovative Technology and Exploring Engineering, 8(46), pp.1865-1869, 2019.

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