Username   Password       Forgot your password?  Forgot your username? 


A Cache Consistency Protocol with Improved Architecture

Volume 14, Number 1, January 2018, pp. 178-185
DOI: 10.23940/ijpe.18.01.p19.178185

Qiao Tian, Jingmei Li, Shuo Zhao, Fangyuan Zheng, Jiaxiang Wang

College of computer science and technology, Harbin Engineering University, Harbin, 150001, China

(Submitted on October 22, 2017; Revised on November 19, 2017; Accepted on December 21, 2017)


With the technical innovation of microprocessors, the application of cache memory prevents the main memory from limiting the development of microprocessors. However, the introduction of Cache also brings the cache coherence problem while the microprocessor performance is being improved. Based on this problem, this paper designs an improved CMP architecture model and proposes a new Cache Coherence Protocol Based on Virtual Bus (CCPBVB). Firstly, the D-Cache virtual bus is added to the architecture to realize the point-to-point consistency transaction transmission, avoiding the bus idle phenomenon caused by the polling query method that the broadcast consistency transaction must follow, while also improving the effective utilization rate of the bus. Then, in order to reduce the access delay caused by the ping-pong phenomenon in the cache memory, a protocol is designed to improve the C hit rate, which combines the write invalid strategy and write update strategy between the private cache to reduce the delay time of the system. The experimental results show that the proposed protocol not only improves the bus utilization, but also reduces the C access delay.


References: 16

1. B. Cuesta, A. Ros, M. E. Gómez and et al, “Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks,”  IEEE Transactions on Computers, vol. 62, no. 3, pp. 482-495, March 2013
2. S. K. Chen, “Study and Implementation of Cache Consistency Protocol in Multi-core Processor,” National Defense University of Science and Technology, pp. 25-40, 2005
3. M. Dalui and B. K. Sikdar, “An efficient test design for CMPs cache coherence realizing MESI protocol,” International Conference on Devices, Circuits and Systems, IEEE, pp. 718-722, 2012
4. S. L. Guo, H.X. Wang, Y. B. Xue and et al, “Hierarchical Cache Directory for CMP,” Journal of Computer Science and Technology, vol. 25, no. 2, pp. 246-256, May 2010   
5. A. Hsia, C. W. Chen and T. J. Liu, “Energy-efficient synonym data detection and consistency for virtual cache,” Microprocessors & Microsystems, vol. 40, no. C, pp. 27-44, February 2016
6. G. M. Li, “Research on Cache Consistency Model in On-chip Multiprocessor Architecture,” University of Science and Technology of China, pp. 57-65, 2013
7. F. J. J. Maturana, C. P. Gómez, E. H. Gómez and et al, “Teaching the cache memory coherence with the MESI protocol simulator,” I.e.s.emilio Canalejo Olmeda Universidad De Córdoba, vol. 98, no. 541, pp. 131-132, January 2006
8. L. G. Menezo, V. Puente and J. A. Gregorio, “Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability,” IEEE International Symposium on High Performance Computer Architecture, pp. 198-209, February 2015 (DOI 10.1109/HPCA.2015.7056033)
9. A. Ros and M. E. Acacio, “DASC-DIR: a low-overhead coherence directory for many-core processors,” Journal of Supercomputing, vol. 71, no. 3, pp. 781-807, March 2015
10. A. Ros and A. Jimborean, “A Dual-Consistency Cache Coherence Protocol,” Parallel and Distributed Processing Symposium, IEEE, pp. 1119-1128, July 2015 (DOI 10.1109/IPDPS.2015.43)
11. A. Ros and A. Jimborean, “A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence,” IEEE Transactions on Parallel & Distributed Systems, vol. 27, no. 11, pp. 3101-3115, February 2016
12. J. W. Shu, Y. Y. Lu, J. C. Zhang and et al, “Research progress on non-volatile memory based storage system,” Science &Technology Review, vol. 34, no. 14, pp. 86-94, June 2016
13. L. S. Selvin and Y.  Palanichamy, “Push-pull cache consistency mechanism for cooper caching in mobile ad hoc environments,” vol. 24, no. 5, pp. 3459-3470, January 2016
14. J. J. Valls, A. Ros, M. E. Gómez and et al, “The Tag Filter Architecture: An energy-efficient cache and directory design,” Journal of Parallel & Distributed Computing, vol. 100, pp. 193-202, February 2017
15. J. J. Valls, A. Ros, J. Sahuquillo and et al, “PS-Dir: a scalable two-level directory cache,” International Conference on Parallel Architectures and Compilation Techniques, pp. 451-452, September 2012 (DOI 10.1145/2370816.2370891)
16. Z. Zhang, “Research and implementation Multi-core cache consistency protocol,” Xi'dian University, pp. 8-11, 2013


Please note : You will need Adobe Acrobat viewer to view the full articles.Get Free Adobe Reader

This site uses encryption for transmitting your passwords.